Minneapolis, MN · University of Minnesota
I take RTL all the way to silicon.
I'm Avyukt (Avi) Raghuvanshi, an Electrical Engineering (Honors) and Physics undergraduate at the University of Minnesota and the founder of Stone Arch Silicon, the university's chip design club. I write SystemVerilog, harden it through open source and commercial flows, and send it to a shuttle. The other half of my week goes to machine learning on gravitational wave and neutrino data with the LIGO, DUNE, and NOvA collaborations.
- diff
- poly
- met1
- met2
- met3
- met4
- met5
Drag to orbit
3D view needs WebGL.
The work is all through the nav.
Three things I spend time on
Chips, signals, and the people learning both.
Silicon
Digital and physical design
RTL in SystemVerilog, hardened through OpenLane and through Synopsys and Cadence, plus the mixed signal boards that carry it.
See the work
Physics
Signals inside detector noise
Low latency classification, uncertainty that knows what it does not know, and losses that will not let a model break the physics.
Read the research
People
Getting undergrads to the fab
Founded Stone Arch Silicon, and helped stand up a network of university groups that now tape out together.
More about me
Most recent silicon
The die on the home page is real.
It is a 2×2 systolic array I designed and hardened end to end. Every number in the strip below came off the run, not off a datasheet.
Live demo
Play with an 8 bit posit.
I am building a posit8 codec in SystemVerilog this term. The same arithmetic is written out in JavaScript on the work page, so you can flip individual bits and watch the regime, exponent, and fraction fields redraw themselves around the change.